Automatic detection of sync polarity in video timing and generation of blanking period indicator from sync information

ABSTRACT

The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] [Not Applicable]

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] [Not Applicable]

SEQUANCE LISTING

[0003] [Not Applicable]

BACKGROUND OF THE INVENTION

[0004] One embodiment of the present invention relates to system andmethod for generating an indicator signal from sync information in videotiming. More specifically, one embodiment of the present inventionrelates to system and method for automatically generating a blankingperiod indicator signal from sync information in video timing.

[0005] Typically digital video signals have a minimum of sixty frames ofvideo per second. Each video frame is composed of horizontal scan lines,where the number of horizontal scan lines in a frame is dependent on theresolution of the system. Each horizontal scan line includes a blankingperiod followed by a series of digital video pixels. More specifically,the horizontal sync (or Hsync) blanking period is used to send timinginformation. The Hsync blanking period is comprised of a Front Porch, aSynchronization Pulse and a Back Porch. Typically there is a verticalsync (or Vsync) blanking period that is comprised of a Front Porch, aSynchronization Pulse and a Back Porch. The Hsync and Vsync blankingperiods typically take about 30% to 40% of the total availablebandwidth.

[0006] Commercial applications utilizing Digital Visual Interface(hereinafter referred to as “DVI”) frequently make significant use ofexisting VESA Computer Display standards. The sequence of timing andvideo data for particular display resolutions and timing is specified inthe VESA Computer Display Monitor Timing standard, Version 1.0, Revision0.8 dated Sep. 17, 1998, incorporated herein by reference. A recentdigital television standard set forth in the CEA-EIA 861 specificationfor high-speed digital interfaces, is also incorporated herein byreference.

[0007] These standards identify a high-speed digital connection,interface or link for visual data types that are display technologyindependent. In one example, the interface provides a connection betweena computer and its display device. In another example, the interfaceprovides a connection between a set top box and a DTV or HDTV. Such aDVI interface enables content to remain in a lossless digital domainfrom creation to consumption; remain display technology independent;support plug and play through hot plug detection, and support EDIDprotocol; and provide digital and analog support in a single connector.

[0008] Further limitations and disadvantages of conventional,traditional and proposed approaches will become apparent to one of skillin the art, through comparison of such systems with the presentinvention as set forth in the remainder of the present application withreference to the drawings.

BRIEF SUMMARY OF THE INVENTION

[0009] Aspects of the present invention may be found in a system andmethod for generating a blanking period indicator signal form syncinformation in video timing. The invention comprises an auto polaritydetect processor adapted to automatically detect the polarity of atleast one sync signal and a generation processor adapted to generate aData Enable (alternatively referred to as “DE”) signal.

[0010] Other aspects, advantages and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings,wherein like numerals refer to like parts.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

[0011]FIG. 1 illustrates a block diagram of an exemplary digital displaylink system;

[0012]FIG. 2 is a stylized example of a digital video frame thatillustrates timing information;

[0013]FIG. 3 illustrates a block diagram of a digital display linksystem with increased digital data capacity in accordance with oneembodiment of the present invention;

[0014]FIG. 4 illustrates video parameters used with configurableregisters in accordance with one embodiment of the present invention;

[0015]FIG. 5 illustrates a high level flow diagram of one method fordetermining the polarity of a sync pulse in accordance with oneembodiment of the present invention;

[0016]FIGS. 6A and 6B illustrate a detailed flow diagram of one methodfor determining the polarity of a sync pulse similar to that illustratedin FIG. 5 in accordance with one embodiment of the present invention;

[0017]FIG. 7 illustrates a high level flow diagram of one method forgenerating a DE signal in accordance with one embodiment of the presentinvention; and

[0018]FIGS. 8A and 8B illustrate a detailed flow diagram of one methodfor generating a DE signal similar to that illustrated in FIG. 7 inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention relates to system and method forautomatically generating a blanking period indicator signal from syncinformation in video timing. In one embodiment, multiple video and audiostreams are transmitted over a DVI link. This includes the transmissionof high quality, multi-channel audio over the DVI link, meeting theneeds of the Consumer Electronics (hereinafter referred to as “CE”)industry. Digital Video, Audio and Auxiliary (alternatively referred toas “DVAAA”) represents the standard for use in the CE industry (amongother industries) for transmitting high quality, multi-channel video,audio and auxiliary data over a digital video or DVI link.

[0020]FIG. 1 illustrates a block diagram of an exemplary digital displaylink system, generally designated 100. In the illustrated embodiment,system 100 includes a digital video source 101 connected to a digitalvideo transmitter 104 via input lines 102. Transmitter 104 encodes thedigital video data for transmission over a digital display link 106. Onthe display side of the system, receiver 108 decodes the digital signalreceived from digital display link 106 and produces a digital videosignal transmitted via output lines 110 to display 112. The overalloperation of the system may be controlled, for example, by finite statemachine 114 using control bus 116.

[0021] Generally, the typical digital video signal includes sixty framesof video per second. Of course, the frame rate may be much lower orhigher than 60 frames. For example, the frame rate may range can be fromabout 25 to 120 frames per second. A video frame is built up from orcomprised of horizontal scan lines, where the number of horizontal linesin a frame is dependent on the resolution of the system.

[0022]FIG. 2 illustrates a stylized example of a digital video framethat illustrates one embodiment of timing information. Each horizontalscan line 201 includes a blanking period or Hsync 203 followed by aseries of digital video pixels (active video) 205. The horizontal blankis used for line timing. It is comprised of three elements: a FrontPorch 207, a sync pulse 209 and a back porch 211. It should beappreciated that the sync pulse 209 may be either positive or negative.

[0023] Additionally, each horizontal scan line includes active video 205comprising three elements: a left border 213, addressable video 215, anda right border 217. The length of the left border 213 and the rightborder 217 is often 0.

[0024] Various elements of a vertical frame are also illustrated in FIG.2. Specifically, the vertical frame is comprised of a front porch 219, avertical sync or Vsync pulse 221, a back porch 223, a top border 225,addressable video 227, and a bottom border 229. Like the Hsync pulse,the Vsync pulse may be either a positive or negative pulse, and the topand bottom borders 225 and 229 respectively are often 0.

[0025] Frames are stacked vertically, so that the entire video stream isa continuum of vertically stacked lines. All lines are then transmitted,in a serial fashion, left to right and top to bottom.

[0026] The sequence of video timing and video data is specified in theVESA and CEAEIA standards referenced above. The VESA Computer Displaystandard is used by digital video links such as DVI links. An exemplaryDVI link has three serial channels for RGB video data and a clockchannel.

[0027] A block diagram of one embodiment of a digital display linksystem with increased digital data capacity, generally designated 300,is illustrated in FIG. 3. In this embodiment, system 300 includes aDVAAA transmitter 302 that transmits information at a first timingstandard to a HDCP engine or device 304. In this embodiment, all inputsto the system 300 may be compliant with the requirements of DVAAA andthe other standards. The system 300 accepts a single stream of videodata, one or more streams of audio data (from 0 to 8 streams forexample), and one or more streams of auxiliary data (from 0 to 4 streamsfor example).

[0028] The HDCP engine 304 encrypts or transforms the informationaccording to an HDCP standard 1.0. In one embodiment, the HDCP engine304 receives the transmitted information and encrypts it. In anotherembodiment, the HDCP engine 304 may be omitted. A DVI transmitter 306communicates with the HDCP engine 304. The DVI transmitter 306 transmitsthe video, audio and auxiliary data stream (with optional encryption) tothe DVI receiver 310 via a digital video communications or DVI link 308.While the HDCP engine 304 and DVI transmitter 306 are illustrated asseparate devices, it should be appreciated that a DVI transmitter withan integrated HDCP encryption engine is also contemplated.

[0029] The DVI receiver 310 communicates the aggregate information, withthe modified sync timing, to a HDCP decryption engine or device 312,where the information is decrypted or reformed (i.e., transformed)according to an HDCP 1.0 standard. In one embodiment, the multiplexedunencrypted data is communicated to a DVAAA receiver 314, where it isdemultiplexed and output as independent video, audio and auxiliary datastreams. The timing input to the DVAAA transmitter 302 is reproduced,and the video stream is also output. While the HDCP decryption engine312 and DVAAA receiver 314 are illustrated as separate devices, itshould be appreciated that a DVAAA receiver with an integrated HDCPencryption engine is also contemplated.

[0030] In one embodiment of the present invention, the DVAAA receiver 34includes an auto polarity detect processor (alternatively referred to asan “auto polarity detector”) adapted to automatically detect thepolarity of the sync signals as described below. In another embodiment,DVAAA receiver 314 includes a DE Generator processor adapted to generatea DE signal as described below. In yet another embodiment, DVAAAreceiver 314 includes both the auto polarity detector processor and theDE generator processor.

[0031]FIG. 4 illustrates typical parameters of a video signal may becollected from the incoming video stream and/or explicitly written toconfigurable registers in accordance with one embodiment of the presentinvention. The parameters include an output HOR_TOTAL generallydesignated 12. HOR_TOTAL 12 corresponds to the VESA defined parameterHOR TOTAL TIME and is measured in pixels. In one embodiment of thepresent invention, HOR_TOTAL is computed from the rising edge of oneHsync pulse to a rising edge of another Hsync pulse. The parameters alsoinclude an output VER_TOTAL generally designated 14. VER_TOTAL 14corresponds to the VESA defined parameter VER TOTAL TIME and is measuredin lines. In one embodiment, VER_TOTAL is computed from the leading edgeof one Vsync pulse to a leading edge of another Vsync pulse.

[0032] The parameters further include HOR_PIXELS generally designated16. This parameter corresponds to the VESA defined parameter HOR PIXELSand is measured in pixels. HOR PIXELS 16 represents the activehorizontal pixel resolution being displayed. The parameters also includeinput VER_PIXELS generally designated 18. VER_PIXELS 18 corresponds tothe VESA defined parameter VER PIXELS and is measured in pixels. Thisregister represents the active vertical pixel resolution beingdisplayed.

[0033] Another input parameter is HBP, generally designated 20. Thisparameter corresponds to the number of pixels in a horizontal back porch(similar to backporch 211) plus the Hsync pulse width (similar to Hsyncpulse 209) in pixels. Yet another input parameter is input VBP,generally designated 22. VBP 22 corresponds to a number of pixels in thevertical back porch (similar to back porch 223) plus the Vsync pulsewidth (similar to Vsync pulse 221) in lines.

[0034] Input/Output parameters in accordance with one embodiment of thepresent invention include HSYNC_POL and VSYNC_POL. HSYNC_POL specificsthe polarity of the Hsync pulse, while VSYNC_POL specifics the polarityof the VSYNC pulse. For both HSYNC_POL and VSYNC_POL. Finally thepresent invention includes an input parameter AUTO_POL_DETECT. In oneembodiment, if AUTO_POL_DETEC is inactive, the HSYNC_POL and VSYNC_POLare input signals used to specify the polarity of HSYNC and VSYNCpulses. In an embodiment in which the AUTO_POL_DETECT is active, theHSYNC_POL and VSYNC_POL are output signals only and the polarity of theHsync and Vsync pulses is automatically detected.

[0035] One embodiment of the present invention also includes an autopolarity detect processor that determines the polarity of the syncpulses. In this embodiment, the period of the sync pulse is shorter thanthe period of the non-sync pulse.

[0036]FIG. 5 illustrates a high level flow diagram of one method ofdetermining the polarity of a sync pulse in accordance with oneembodiment of the present invention. In this embodiment, the polarity ofthe sync pulse is determined using an auto polarity detect processorsimilar to that described previously. The auto polarity detect processorcounts the number of pixels or lines of a sync pulse as illustrated byblock 30. The processor then determines the polarity of the sync pulseas illustrated by block 32.

[0037]FIGS. 6A and 6B illustrate a detailed flow diagram of one methodof determining the polarity of a sync pulse in accordance with oneembodiment of the present invention. In this embodiment, the polarity ofthe sync pulse is determined using an auto polarity detect processorsimilar to that described previously. The test counter is set to zero asillustrated by block 34. The auto polarity detect processor detects afirst sync pulse edge as illustrated by block 36.

[0038] the sync pulse edge is detected, the test counter begins toincrement as illustrated by block 40. In one embodiment, it iscontemplated that the test counter is incremented to count the number ofpixels (Hsync for example) or lines (Vsync for example) until a secondedge of the sync signal is detected as illustrated by diamond 42. If theedge of the second edge of the sync signal is not detected, theprocessor continues to increment the test counter until the second edgeof the sync signal is detected. While one embodiment of the presentinvention detects one or more edges of the sync signals, it iscontemplated that the processor may detect transitions of the signals.

[0039] The auto polarity detect processor decrements the test counter asillustrated by block 44. The processor determines if a third edge on thesync signal is detected as illustrated by diamond 46. If this edge isdetected, the processor determines that the pulse just ended and thepolarity of the pulse is the level of the sync signal prior to the thirdedge as illustrated in block 50.

[0040] the sync pulse edge is not detected, the auto polarity detectprocessor determines if the counter has reached (is equal to) zero asillustrated by diamond 48. If the counter has not reached zero, the testcounter is decremented as illustrated by block 44. If however, thecounter has reached zero, then the next edge is a start of the pulse.The polarity of the pulse is the inverse of the polarity of the syncsignal when the counter reaches 0 as illustrated previously by block 50.

[0041] The present invention also includes a DE generation processor,which performs the following steps to generate a DE signal. FIG. 7illustrates a high level flow diagram of one method for generating a DEsignal in accordance with one embodiment of the present invention. Thegeneration processor determines the values of HOR_TOTAL and VER_TOTAL asillustrated by block 52. The processor generates the horizontal H_DE andvertical V_DE, and produces the H_DE and V_DE as illustrated by blocks54 and 56 respectively.

[0042]FIGS. 8A and 8B illustrate a detailed flow diagram of one methodfor generating a DE signal similar to that illustrated in FIG. 7 inaccordance with one embodiment of the present invention. The polarity ofthe sync pulses are determined as illustrated by block 57. The DEgeneration processor detects a leading edge of the sync pulse anddetermines the values of HOR_TOTAL and VER_TOTAL as illustrated byblocks 58 and 60. All the relevant information is loaded into a registeras illustrated by block 62. The DE generation processor generates thehorizontal H_DE by preloading a countdown counter with the value HBP atthe leading edge of the Hsync pulse at illustrated by block 64A. It iscontemplated that the leading edge of the Hsync pulse may be eitherrising or falling depending on the setting of the HSYNC_POL.

[0043] The countdown counter counts down or is decremented to zero asillustrated by block 66A. At zero H_DE is set high and the countdowncounter is preloaded with a value in HOR_PIXELS as illustrated by blocks68A and 70A. When the countdown counter reaches zero, H_DE is set low asillustrated by block 74A. The horizontal H_DE is thus generated, and thecountdown counter is preloaded with the value HVP at the leading edge ofthe Hsync pulse. In one embodiment, the horizontal H_DE is generated ina repetitive manner.

[0044] order to generate the V_DE signal the countdown counter ispreloaded with the value VBP at the leading edge of the Vsync pulse asillustrated by block 64B. It is again contemplated that the leading edgeof may be either rising or falling depending on the setting ofVSYNC_POL. The countdown counter then counts or is decremented to zeroas illustrated by block 66B. HSYNC_POL and VSYNC_POL may be setexplicitly in one embodiment of the present invention. In anotherembodiment, the polarities may be determined as provided previously.

[0045] zero V_DE is set high and a countdown counter is preloaded with avalue in HOR_PIXELS as illustrated by blocks 68B and 70B. When thecountdown counter reaches zero, V_DE is set low as illustrated by block74B. The vertical V_DE is generated, and the countdown counter ispreloaded with the value VBP at the leading edge of the Vsync pulse. Inone embodiment, the vertical V_DE is generated in a repetitive manner.

[0046] Finally V_DE and H_DE are logically ADDED to produce DE asillustrated by block 78. In one embodiment of the present invention, theedges of the Hsync and Vsync pulses are coincident. However, otherembodiments are contemplated were the Hsync and Vsync pulses are notcoincident. Further, embodiments are contemplated wherein the polarityof the Hsync and Vsync pulses are specified by HSYNC_POL and VSYNC_POLrespectively. For example, interlaced timings.

[0047] Many modifications and variations of the present invention arepossible in light of the above teachings. Thus, it is to be understoodthat, within the scope of the appended claims, the invention may bepracticed otherwise than as described hereinabove.

What is claimed and desired to be secured by Letters Patent is:
 1. Amethod for determining a polarity of a sync pulse comprising:determining a count of the sync pulse using a counter; and determiningthe polarity of the sync pulse using said count.
 2. The method of claim1, wherein determining said count includes incrementing said counteruntil a next edge is detected.
 3. The method of claim 2, whereindetermining said count includes counting a number of pixels for an Hsyncpulse.
 4. The method of claim 2, wherein determining said count includescounting a number of lines for a Vsync pulse.
 5. The method of claim 2,wherein the polarity of the sync pulse is equal to a level of a syncpulse.
 6. The method of claim 5, wherein the polarity of the sync pulseis equal to said level of said sync pulse prior to a third edge of async pulse is detected.
 7. The method of claim 5, including decrementingsaid counter until a third edge of a sync pulse is detected.
 8. Themethod of claim 1, wherein the polarity of the sync pulse is equal to aninverse of a polarity of a sync signal.
 9. The method of claim 8,wherein the polarity of the sync pulse is equal to said inverse of saidpolarity of said sync signal when said counter reaches zero.
 10. Themethod of claim 8, including decrementing said counter until saidcounter reaches zero.
 11. The method of claim 1, wherein a polarity of ahorizontal sync pulse is explicitly set.
 12. The method of claim 1,wherein a polarity of a vertical sync pulse is explicitly set.
 13. Amethod for determining a polarity of generating a blanking periodindicator signal comprising: determining a count of the sync pulse usinga counter; and determining the polarity of the sync pulse using saidcount.
 14. A method for determining a polarity of sync pulsescomprising: setting a test counter to zero; detecting an edge of atleast one of said sync pulses; incrementing said test counter until asecond edge of at least one of said sync pulses is detected; anddecrementing said test counter, determining the polarity of the syncpulses.
 15. The method of claim 14, wherein the polarity is equal to alevel of a sync pulse prior to a third edge of at least one of said syncpulses is detected.
 16. The method of claim 15, including decrementingsaid test counter until said third edge is detected.
 17. The method ofclaim 14, wherein the polarity is equal to an inverse of a polarity ofat least one of said sync pulses.
 18. The method of claim 17, whereinthe polarity is equal to said inverse when said test counter reacheszero.
 19. The method of claim 17, including decrementing said testcounter until said test counter reaches zero.
 20. The method of claim14, wherein a polarity of a horizontal sync pulse is explicitly set. 21.The method of claim 14, wherein a polarity of vertical sync pulse isexplicitly set.
 22. A method for generating a blanking period indicatorsignal comprising: setting a test counter to zero; detecting an edge ofat least one of said sync pulses; incrementing said test counter until asecond edge of at least one of said sync pulses is detected; anddecrementing said test counter, determining the polarity of the syncpulses.
 23. A system for generating a blanking period indicator signalcomprising: an auto polarity detect processor adapted to automaticallydetect the polarity of at least one sync signal; and a generationprocessor adapted to generate a DE signal.